Clock data recovery apparatus and method and phase detector
US9685962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0332
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.