Fractional dividing module and related calibration method
US9685966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Oct 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.