Asynchronous successive approximation register analog-to-digital converter circuit and method for configuring the same
US9685972B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Jun 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an asynchronous successive approximation register analog-to-digital conversion (ASAR ADC) circuit, including: a comparator circuit, an XOR gate circuit, an ASAR logic circuit, a metastable state detection (MD) circuit, a capacitor, and a digital-to-analog converter (DAC) circuit. The comparator circuit has a first input terminal connected to an analog signal, a first output terminal of the comparator circuit respectively connected to a first input terminal of the ASAR circuit and a first input terminal of the XOR gate circuit, a second output terminal of the comparator circuit respectively connected to a second input terminal of the ASAR gate circuit and a second input terminal of the XOR gate circuit, and an enable signal input terminal connected to a control signal output terminal of the ASAR logic circuit. The XOR gate circuit has an output terminal connected to a third input terminal of the ASAR logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.