Dual-rail power equalizer
US9690365B2 · kind B2 · utility
3Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.