Mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof
US9690719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2014 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Sep 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45579
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.