Patent · US Active

Method and apparatus for system design verification

US9690888B2 · kind B2 · utility

2Cited by

3References

9Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Xiangdong Lu · Jingwei, CN
Wangsheng Mei · Suzhou, CN
Prashant U. Naphade · Austin, US

Key dates

Filing date	Oct 20, 2015
Grant date	Jun 27, 2017
Priority date	—
Expiry date	Dec 7, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as TCL) and a testbench including the design under test and operating with a Hardware Descriptor Language (such as SystemVerilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on ‘C’.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.