Automatically enhanced visual process repair using process superposition and ugliness indicators
US9691022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2014 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Nov 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09B7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention generally relates to systems and methods for visual process analysis. The disclosed techniques can include: obtaining a theoretical and an empirical process model, generating a theoretical process layout corresponding to the theoretical process model, where the theoretical process layout is generated using a layout algorithm, generating an empirical process layout corresponding to the empirical process model, where the empirical process layout is generated using the layout algorithm, superposing the empirical process layout onto the theoretical process layout, such that a superposition layout is generated, annotating the superposition layout based on ugliness indicators, such that an annotated superposition layout is generated, and causing the annotated superposition layout to be displayed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.