Multi-context configuration memory
US9691476B2 · kind B2 · utility
1Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Aug 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.