Semiconductor memory device

US9691786B1 · kind B1 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Masaki Tsuji · Fukaya, JP
• Hideaki Aochi · Kawasaki, JP
• Jun Fujiki · Yokohama, JP

Key dates

• Filing date: Aug 31, 2016
• Grant date: Jun 27, 2017
• Expiry date: Aug 31, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/27

Abstract

A semiconductor memory device according to an embodiment includes: a first semiconductor layer; and a memory cell array on the first semiconductor layer, the memory cell array including a source line, a second semiconductor layer, and a conductive layer, those are sequentially disposed in a first direction and the memory cell array further including a third semiconductor layer which is columnar and extends in the first direction and a charge accumulation film disposed between the conductive layer and the third semiconductor layer, wherein the second semiconductor layer includes a first impurity region of a first conductivity type disposed at a position of the third semiconductor layer as viewed from the first direction and a second impurity region adjacent to the first impurity region which has a second conductivity type different from the first conductivity type.