Semiconductor device, manufacturing method thereof, and electronic device
US9691905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Jun 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.