Pulse width widener and a memory system including the same
US9692400B2 · kind B2 · utility
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6References
19Claims
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Key dates
| Filing date | Jun 20, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Jun 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse width widener includes a delay circuit, a processing circuit, and a latch circuit. The delay circuit generates a first signal by delaying an input signal including a first pulse by a delay time. The processing circuit generates a second signal, and the second signal includes information of a second pulse that is temporally extended from the first pulse when a width of the first pulse is smaller than the delay time, based on the first and second signals. The latch circuit stores the second signal and outputs the second pulse as an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.