Transition glitch suppression circuit
US9692417B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Aug 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transition glitch suppression circuit can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal. The transition glitch suppression circuit has a delay element that can delay the input signal by the time delay to generate a delayed input signal. The transition glitch suppression circuit also has first and second logic circuits that process the input signal and the delayed input signal to generate corresponding outputs. A multiplexer provides the output signal for the suppression circuit by selecting between the output of the first logic circuit and the output of the second logic circuit based on the value of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.