Compact logic evaluation gates using null convention
US9692419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Nov 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09425
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL complement input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.