Delta-Sigma ADC with wait-for-sync feature
US9692446B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/324
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip containing a Delta-Sigma (ΔΣ) filter module for a ΔΣ analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ΔΣ filter that is connected to receive a digital data stream created by a ΔΣ modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.