Patent · US Active

Memory controller with interleaving and arbitration scheme

US9697118B1 · kind B1 · utility

1Cited by

6References

18Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Vivek Singh · Monmouth Junction, US
Navdeep Gill · San Jose, US
Stephan Herrmann · Borgo San Lazzaro, DE
Sumit Mittal · Sidhauli, IN

Key dates

Filing date	Dec 9, 2015
Grant date	Jul 4, 2017
Priority date	—
Expiry date	Mar 20, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1008
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.