Execution-aware memory protection

US9697142B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Patrick Koeberl · Hähnlein, DE
• Steffen Schulz · Darmstadt, DE

Key dates

• Filing date: Jun 24, 2016
• Grant date: Jul 4, 2017
• Expiry date: Jun 24, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F21/79
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Execution-Aware Memory protection technologies are described. A processor includes a processor core and a memory protection unit (MPU). The MPU includes a memory protection table and memory protection logic. The memory protection table defines a first protection region in main memory, the first protection region including a first instruction region and a first data region. The memory protection logic determines a protection violation by a first instruction when 1) an instruction address, resulting from an instruction fetch operation corresponding to the first instruction, is not within the first instruction region or 2) a data address, resulting from an execute operation corresponding to the first instruction, is not within the first data region.