Memory and interface circuit for bit line of memory
US9697890B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit is provided. A NMOS transistor is coupled between a first bit line and a ground. A logic gate is coupled between a gate of the NMOS transistor and a second bit line. A keeper controls a voltage level of the second bit line according to a reference voltage. A tracking circuit includes a plurality of reference bit cells and a pull-up device coupled to a reference bit line. Each reference bit cell is coupled to a read word line. When a bit cell coupled to the second bit line is accessed by a specific read word line, the reference bit cell coupled to the specific read word line drains a current from the pull-up device. The tracking circuit provides the reference voltage according to the current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.