Integrated electronic package and stacked assembly thereof
US9698104B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.