Multi-gate and complementary varactors in FinFET process
US9698146B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Mar 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.