Vertical memory devices
US9698151B2 · kind B2 · utility
15Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Jun 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.