Array substrate, method for manufacturing the same, and display apparatus
US9698178B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 30, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Apr 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an array substrate includes coating a photoresist onto an insulation layer including a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern. The method further includes exposing the photoresist to form a photoresist partially-reserved region and a photoresist unreserved region. The method further includes performing a first etching process to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, to form an intermediate hole. The method further includes performing a second etching process to form the first via hole and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.