Power MOS transistor and manufacturing method therefor
US9698248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so as to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.