Patent · US Active

Method for fabricating CMOS compatible contact layers in semiconductor devices

US9698309B2 · kind B2 · utility

0Cited by

6References

6Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Celso Cavaco · Leuven, BE
Brice De Jaeger · Leuven, BE
Marleen Van Hove · Blanden, BE
Vasyl Motsnyi · Leuven, BE

Key dates

Filing date	Jan 6, 2016
Grant date	Jul 4, 2017
Priority date	—
Expiry date	Jan 6, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10H20/825
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.