System and method for clock generation with an output fractional frequency divider
US9698800B2 · kind B2 · utility
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2References
6Claims
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Key dates
| Filing date | Mar 17, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Mar 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/486
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.