Half-rate clock data recovery circuit
US9698969B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A half-rate clock data recovery circuit includes: a voltage-controlled oscillator (VCO) for generating a data sampling clock and an edge sampling clock according to a control voltage; an adjusting circuit for dynamically controlling the VCO to adjust the phase difference between the data sampling clock and the edge sampling clock to be different from 90 degrees in multiple test periods; and a control circuit for instructing the adjusting circuit to respectively utilize different control value combinations to control the VCO in the multiple test periods, and for recording multiple recovered-signal quality indicators respectively corresponding to the multiple test periods. Afterwards, the control circuit instructs the adjusting circuit to utilize a control value combination corresponding to the best quality indicator among the multiple recovered-signal quality indicators to control the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.