Instruction emulation processors, methods, and systems
US9703562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2013 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Feb 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30189
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.