Instruction and logic for processing text strings
US9703564B2 · kind B2 · utility
2Cited by
41References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2014 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jul 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor to perform a string comparison instruction. The processor includes a decoder to decode the string comparison instruction. The packed comparison instruction is to have an immediate that is to be used to control performance of the string comparison instruction. The immediate includes a first set of two bits, a second set of two bits, a third set of two bits, and a fourth bit. The processor also includes an execution unit coupled with the decoder to execute the packed comparison instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.