Method, apparatus, and system for improving inter-chip and single-wire communication for a serial interface
US9703737B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jun 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stage of a clock signal and. Further, the inverter provides a second path to a first ground line on a second stage of a clock signal. The bus interface link couples the master device to a slave device. Additionally, a bi-directional communications line is coupled to the bus interface link. A gating component provides a second ground line to the power supply through the first path. Furthermore, a receiver determines bit values from a plurality of clock data signals transmitted from the master device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.