Method and system for simulating multiple processors in parallel and scheduler
US9703905B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | May 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.