Non-valatile semiconductor memory device and location based erasure methods
US9704579B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jul 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device comprising a control circuit is provided, the control circuit performing a data erasure by applying predetermined erase voltages to predetermined blocks of a memory cell array including memory cells disposed on each intersection of a plurality of word lines and a plurality of bit lines, and the control circuit applying the erase voltages to the memory cells to erase data by applying word line voltages different to each other to even-numbered word lines and odd-numbered word lines of the memory cell array except to an edge part thereof, and by applying a voltage different to the word line voltages to the word line in the edge part of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.