Memory circuit with assist circuit trimming
US9704599B1 · kind B1 · utility
4Cited by
10References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a memory array comprising a plurality of bits, wherein a first bit of the plurality of bits is coupled to a first assist circuit; a test engine, coupled to the memory array, and configured to examine whether each bit is functional; and an assist circuit trimming (ACT) circuit, coupled to the memory array and the test engine, and in response to the examination, configured to selectively activate the first assist circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.