Method of forming key patterns and method of fabricating a semiconductor device using the same
US9704721B2 · kind B2 · utility
2Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jan 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a method of forming key patterns and a method of fabricating a semiconductor device using the same. The method of forming key patterns may include forming gate and key patterns on a cell region and a scribe lane region, respectively. Here, the key patterns may be formed to have a large width and a larger pitch than those of the gate patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.