Integrated device having multiple transistors
US9704858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jul 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/665
Abstract
An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.