Display circuitry with reduced metal routing resistance
US9704888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6723
Abstract
A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.