Memory effect reduction using low impedance biasing
US9705454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jul 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/69
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.