Synchronization of endpoints using tunable latency
US9705620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Mar 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.