Integrated circuit with continuously adaptive equalization circuitry
US9705708B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for supporting a high-speed communications link is provided. The integrated circuit may include equalization circuitry having a continuous time linear equalizer (CTLE) circuit, a decision feedback equalizer (DFE) circuit, and associated adaptation logic for controlling the CTLE circuit and the DFE circuit. The adaptation logic may include an error minimization adaptation circuit operable to generate at least a first post-cursor value, a signal amplitude detection circuit operable to generate a main cursor value, and a CTLE adaptation circuit configured to compute a ratio between the first post-cursor value and the main cursor value. The CTLE adaptation circuit may compare the computed ratio to predetermined values to determine whether or not to adjust the peaking gain of the CTLE circuit to help minimize inter-symbol interference for signals traveling through the high-speed communications link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.