Method and device for differential signal channel length compensation in electronic system
US9706642B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2010 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Aug 1, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to providing a time delay to a shortened trace in a differential microstrip trace pair. By adding back metal to a ground plane associated with a DC blocking capacitor, a time delay can be added to the shortened trace. The cutout associated with the longer trace remains unaltered. In a further embodiment, both cutouts can be modified with the addition of metal, with the cutout associated with the shorter trace receiving more metal than the other cutout. In a further embodiment of the present invention, a cutout associated with a connector can be modified to add back metal in the cutout. The cutout associated with the shorter trace is modified while the other cutout is left unchanged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.