Reducing latency for pointer chasing loads
US9710268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2014 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Oct 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.