Endian configuration memory and ECC protecting processor endianess mode circuit
US9710318B2 · kind B2 · utility
6Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Jan 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.