Decimation synchronization in a microphone
US9711166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2014 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Nov 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2499/11
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An external clock signal having a first frequency is received. A division ratio is automatically determined based at least in part upon a second frequency of an internal clock. The second frequency is greater than the first frequency. A decimation factor is automatically determined based at least in part upon the first frequency of the external clock signal, the second frequency of the internal clock signal, and a predetermined desired sampling frequency. The division ratio is applied to the internal clock signal to reduce the first frequency to a reduced third frequency. The decimation factor is applied to the reduced third frequency to provide the predetermined desired sampling frequency. Data is clocked to a buffer using the predetermined desired sampling frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.