Memory device having different data-size access modes for different power modes
US9711192B2 · kind B2 · utility
3Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.