Patent · US Active

Memory circuit

US9711244B1 · kind B1 · utility

0Cited by

4References

16Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Yuen H. Chan · Poughkeepsie, US
Silke Penth · Holzgerlingen, DE
David Edward Schmitt · Rochester, US
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Jun 14, 2016
Grant date	Jul 18, 2017
Priority date	—
Expiry date	Jun 14, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/79
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

It is provided a memory circuit comprising n inputs; n+1 columns, wherein each column is connected to a plurality of memory cells; wherein the i-th (1≦i≦n−1) column is configured to be conductive connectable to the i-th input or to the (i+1)-th input or neither to the i-th input nor to the (i+1)-th input; a first FET and a second FET in series configured for connecting the i-th column to a defined voltage level; wherein a first gate signal renders the first FET conductive, if the i-th column is not in conductive connection with the i-th input; wherein a second gate signal renders the second FET conductive, if the i-th column is not in conductive connection with the (i+1)-th input.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.