Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology
US9711471B2 · kind B2 · utility
0Cited by
5References
15Claims
0Family size
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Key dates
| Filing date | Apr 18, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Apr 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.