3D NAND device and fabrication method thereof
US9711529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | May 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.