LTPS array substrate

US9711540B2 · kind B2 · utility

Assignee

• TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED · CN

Inventors

• Cong Wang · Tangxia, CN
• Peng Du · Tangxia, CN

Key dates

• Filing date: Jan 13, 2015
• Grant date: Jul 18, 2017
• Expiry date: Feb 16, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/481

Abstract

An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate electrode line and a common electrode line, an insulation layer, a drain electrode and a source electrode, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. The bottom transparent conductive layer, the protection layer, and the top transparent conductive layer are sequentially stacked on the planarization layer. The patternized poly-silicon layer includes a first portion and a second portion. The drain electrode includes an extension section extending therefrom and opposite to the second portion.