Method of making thin film transistor array and source/drain contact via-interconnect structures formed thereby
US9711602B2 · kind B2 · utility
1Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Feb 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application discloses a thin film transistor comprising active layer on a base substrate; an insulating layer over the active layer, the insulating layer comprising a source via and a drain via, each of which extending through the insulating layer; a source electrode within the source via in contact with the active layer; and a drain electrode within the drain via in contact with the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.