Process variation power control in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US9712168B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for process variation power control in three-dimensional integrated circuits (3DICs) are disclosed. In an exemplary aspect, at least one process variation sensor is placed in each tier of a 3DIC. The process variation sensors report information related to a speed characteristic for elements within the respective tier to a decision logic. The decision logic is programmed to weight output from the process variation sensors according to relative importance of logic path segments in the respective tiers. The weighted outputs are combined to generate a power control signal that is sent to a power management unit (PMU). By weighting the importance of the logic path segments, a compromise voltage may be generated by the PMU which is “good enough” for all the elements in the various tiers to provide acceptable performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.