Incremental preloading in an analog-to-digital converter
US9712181B1 · kind B1 · utility
5Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 23, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Sep 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.