Quadrature demodulator for a very high bit rate RFID receiver
US9712211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3845
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A quadrature demodulator not requiring analog mixers. The demodulation is made using a first integrator and a second integrator which are controlled by square logic signals at twice the frequency of the carrier, the received signal being alternatively integrated by the first integrator and the second integrator over periods of time equal to a quarter period of time of the carrier frequency. The samples of the first and second integrators are sampled and subtracted from each other. The successive samples are combined in a first and a second combining module for providing in-phase and quadrature component samples. This demodulator can further be provided with a synchronization module IQ and a symbol synchronization module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.